The present invention relates to a phase locked loop (PLL) circuit and, more particularly, a PLL circuit having a relatively wide frequency oscillation range.
In recent years, efforts have been made to achieve a higher density of information recorded in a recording medium such as a digital data storage (DDS), a digital versatile disk (DVD), or a compact disk (CD), as well as in a recording device such as a hard disk drive (HDD), and to achieve a higher speed for reading/writing information. A recording/reproducing device has been presented for surely recording information at a writing speed enough for recording, and reading information at a reading speed higher than the writing speed. In a recording/reproducing device using a disk recording medium, a reading speed is greatly changed according to a head position in a radial direction of the disk. Thus, a PLL circuit for generating a clock signal for reading/writing must have a wide frequency oscillation range, and jitters of the PLL circuit are required to be reduced.
FIG. 1 is a schematic block diagram of a conventional PLL circuit 61. The PLL circuit includes a phase comparator 62, a charge pump 63, a loop filter 64, a voltage/current converter (referred to as V/I converter, hereinafter) 65, a current controlled oscillator (CCO or ICO (referred to as ICO, hereinafter)) 66, and a frequency divider 67.
The phase comparator 62 compares a phase of a reference signal fr with a phase of a frequency-divided signal supplied from the frequency divider 67, and generates an up signal UP and a down signal DN each having a pulse width corresponding to a phase difference.
The charge pump 63 generates a charge pump output signal SCP having a current corresponding to the up signal UP and the down signal DN supplied from the phase comparator 62.
The loop filter 64 is a low-pass filter (LPF) including a resistor and a capacitor, and removes a high-frequency component contained in the charge pump output signal SCP, and generates a filtered output signal SLF having a voltage.
The V/I converter 65 performs voltage/current conversion for the filtered output signal SLF, and generates a control signal SI having a current corresponding to a voltage of the filtered output signal SLF.
The ICO 66 generates an oscillation frequency signal fi having a frequency corresponding to a current of the control signal SI, supplies this oscillation frequency signal fi as a PLL oscillation signal to an external circuit (not shown), and the frequency divider 67.
The frequency divider 67 divides a frequency of the oscillation frequency signal fi of the ICO 66 into a predetermined frequency-divided value (ratio of divided frequency), and generates a frequency-divided signal fp. The frequency-divided signal fp is fed back to the phase comparator 62.
In place of the V/I converter 65 and the ICO 66, a voltage controlled oscillator (VCO) may be used for generating an oscillation frequency signal fi having a frequency corresponding to a voltage of the filtered output signal SLF of the loop filter 64.
In the PLL circuit 61, if a frequency of the oscillation frequency signal fi is smaller than a desired locked frequency, a frequency of the frequency-divided signal fp becomes smaller than that of the reference signal fr, generating a phase difference between the frequency-divided signal fp and the reference signal fr. In this case, the phase comparator 62 generates an up signal UP having a pulse width larger than that of a down signal DN. In response to the up signal UP, the charge pump 63 charges the loop filter 64 for a period longer than a discharging period. Accordingly, a voltage of the filtered output signal SLF of the loop filter 64 increases. The V/I converter 65 generates a control signal SI having a current corresponding to the voltage of the filtered output signal SLF. Then, in response to the control signal SI, the ICO 66 increases a frequency of the oscillation frequency signal fi.
If a frequency of the oscillation frequency signal fi is larger than the desired locked frequency, a frequency of the frequency-divided signal fp becomes larger than that of the reference signal fr. In this case, the phase comparator 62 generates an up signal UP having a pulse width smaller than that of a down signal DN. In response to the up signal UP, the charge pump 63 charges the loop filter 64 for a period shorter than a discharging period. Accordingly, a voltage of the filtered output signal SLF of the loop filter 64 decreases. The V/I converter 65 generates a control signal SI by performing voltage/current conversion for the filtered output signal SLF. Then, in response to the control signal SI, the ICO 66 reduces a frequency of the oscillation frequency signal fi.
By repeating the above-mentioned operations, an oscillation frequency signal fi having a frequency matched (locked) with the desired frequency is output from the ICO 66.
FIG. 2 is a schematic block diagram showing a conventional timing recovery PLL circuit (referred to as TR-PLL, hereinafter) 71. The TR-PLL 71 includes, in addition to the components of the PLL circuit 61 of FIG. 1, a timing recovery control circuit (referred to as TR control circuit, hereinafter) 72, a current controller 73, and an ICO 74. Components of FIG. 2 similar to those of FIG. 1 are denoted by similar reference numerals.
A V/I converter 65a receives a filtered output signal SLF from a loop filter 64, and generates a control signal SI1 for controlling an oscillation frequency of a first ICO 66, and a control signal SI3 for controlling an oscillation frequency of a second ICO 74 by performing voltage/current conversion for the filtered output signal SLF. A current of the control signal SI1 is substantially equal to that of the control signal SI3.
The TR control circuit 72 receives a reading signal RD, and detects a phase difference of the reading signal RD with respect to an oscillation frequency signal ftr of the second ICO 74 by using the reading signal RD, thus generating a control signal STR. The reading signal RD is a signal read from a recording medium (not shown) according to the oscillation frequency signal ftr output from the second ICO 74.
The current controller 73 includes a digital/analog converter (DAC). The current controller 73 corrects a current I3 of the control signal SI3 in accordance with the control signal STR output from the TR control circuit 72, and generates a control signal SI4 having a corrected current I4. For example, the TR control circuit 72 generates a control signal STR having a corrected value d corresponding to a phase difference of the reading signal RD. In response to the control signal STR, the current controller 73 corrects the current I3 of the control signal SI3, and generates a control signal I4 having a corrected current I4 {I4=I3xc3x97d}.
The second ICO 74 generates an oscillation frequency signal ftr having a frequency corresponding to the corrected current I4 of the control signal SI4 from the current controller 73. Then, data recorded in the recording medium is read in accordance with the oscillation frequency signal ftr.
Therefore, a frequency of the reading signal RD read from the recording medium is matched (locked) with that of the oscillation frequency signal ftr of the second ICO 74, stabilizing a reading operation.
In the PLL circuit 61 of FIG. 1, an oscillation frequency of the ICO 66 corresponds to a current of the control signal SI of the V/I converter 65 (i.e., voltage of the filtered output signal SLF of the loop filter 64). In other words, when a current of the control signal SI (voltage of the filtered output signal SLF) decreases, an oscillation frequency of the ICO becomes small. Thus, in the case where the current of the control signal SI (voltage of the filtered output signal SLF) is lowered to a predetermined value or lower, the ICO 66 is not oscillated in some cases.
In addition, when the ICO 66 is oscillated by a relatively small current (voltage), phase fluctuation of an oscillation frequency caused by noise, i.e., jitters, increase. Consequently, the oscillation of the ICO 66 becomes unstable, causing, for example unlocking.
FIG. 3 is a graph showing a relation between a current and an oscillation frequency in an ICO. As shown in FIG. 3, a fluctuation width in a current by noise is set to xcex94I. When a current is relatively large, a jitter xcex94F1 is smaller than a jitter xcex94F2 when a current is relatively small. That is, jittering increases as a current decreases. One of the other factors for an increase in a jitter, may be use of, for example transistors shifted from a saturated region as the ICO 66. If a current of a certain level is not flowing in the transistor, the transistor enters a state of being shifted from the saturated region (unsaturated region). It is generally known that in this state, an operational characteristic of the transistor becomes unstable. Accordingly, when a current decreases, a control characteristic of the ICO 66 becomes unstable, increasing a jitter. Consequently, it was impossible to increase an oscillation frequency of the ICO 66.
Further, if a current having a certain value or higher is supplied to the ICO 66 (indicated by SAT in FIG. 3), almost no changes occur in an oscillation frequency even if a current increases. In this case, a jitter decreases, but it is difficult to change the oscillation frequency of the ICO 66.
Various problems described above occur even in the TR-PLL 71 of FIG. 2. Also, it is generally known that in the TR-PLL 71, if the first and second ICO 66 and ICO 74 are physically close to each other, an oscillation frequency of the second ICO 74 is drawn into an oscillation frequency of the first ICO 66 in a particular frequency band. That is, the oscillation frequency of the second ICO 74 cannot be changed. Thus, normally, by interconnecting the V/I converter 65a and the current controller 73 with a relatively long wire L2, a larger distance is set between the first and second ICO 66 and ICO 74. However, use of such a long wire L2 makes it easy for the wire L2 to be affected by noise, consequently increasing a jitter in the second ICO 74.
Japanese Laid-Open Patent Publication No. 6-104748 discloses a PLL circuit, which includes a plurality of VCO (or ICO) having center frequencies different from each other, and a selector for selecting one of the VCOs. With the configuration of this PLL circuit, if a voltage (current in the case of ICO) decreases to a predetermined value or lower, or oscillation is impossible in the VCO, an oscillation frequency range of the PLL circuit increases by selecting another VCO to cause oscillation. In addition, if a jitter is large even when oscillation can be performed by the VCO, the jitter can be reduced by similarly switching to another VCO.
However, the presence of the plurality of VCO (or ICO) has a drawback of increasing a size of the PLL circuit. Especially, in the case of the TR-PLL 71 of FIG. 2, since the first and second ICO 66 and ICO 74 ideally having similar characteristics are provided, the circuit size is increased more. That is, in the case of the TR-PLL 71, if the PLL circuit 61 of FIG. 1 includes ICO amounting to n in number, (2xc3x97n) pieces of ICO are necessary.
In addition, Japanese Laid-Open Patent Publication No. 11-177416 discloses a PLL circuit, which detects a device characteristic change of a VCO (or ICO) control signal caused by manufacturing condition fluctuation, and adds an offset signal based on a result of the detection to the VCO control signal. With the configuration of this PLL circuit, by reducing changes in the VCO control characteristics caused by manufacturing condition fluctuation, power supply fluctuation, and temperature changes, a fluctuation range xcex94I (see FIG. 3) of an oscillation frequency control current of the ICO by noise is reduced, thus reducing an effect on an oscillation frequency.
The PLL circuit described in Japanese Laid-Open Patent Publication No. 11-177416 includes a circuit (e.g., ADC) for generating an offset signal. Thus, this PLL circuit has had a drawback of increasing its circuit size. Moreover, even if fluctuation in the oscillation frequency control current of the ICO caused by manufacturing conditions and the like can be reduced, it has been impossible to increase an oscillation frequency range.
An object of the present invention is to provide a PLL circuit having a wide oscillation frequency range, and capable of reducing a jitter.
In a first aspect of the present invention, a PLL circuit including a phase comparator for generating a phase difference signal by comparing a phase of a reference signal with a phase of a comparison signal is provided. An oscillator is connected to the phase comparator to generate an oscillation frequency signal having an oscillation frequency according to a control signal having one of a current and a voltage corresponding to the phase difference signal. A detection circuit generates a detection signal by detecting one of the current and the voltage of the control signal. A signal generation circuit is connected to the detection circuit to generate a signal for changing the oscillation frequency of the oscillator such that one of the current and the voltage of the control signal is within a predetermined range in accordance with the detection signal.
In a second aspect of the present invention, the PLL circuit including a phase comparator for generating a phase difference signal by comparing a phase of a reference signal with a phase of a comparison signal is provided. An oscillator is connected to the phase comparator to generate an oscillation frequency signal having an oscillation frequency according to a control signal having one of a current and a voltage corresponding to the phase difference signal. A first frequency divider is connected to the oscillator to generate a PLL oscillation frequency signal by frequency-dividing the oscillation frequency signal with a first frequency dividing value. A detection circuit generates a detection signal by detecting one of the current and the voltage of the control signal. A signal generation circuit is connected to the detection circuit to generate a signal for changing the oscillation frequency of the oscillator such that one of the current and the voltage of the control signal is within a predetermined range in accordance with the detection signal.
In a third aspect of the present invention, a PLL circuit including a phase comparator for generating a phase difference signal by comparing a phase of a reference signal with a phase of a comparison signal is provided. A first oscillator generates a first oscillation frequency signal having an oscillation frequency according to a first control signal having one of a current and a voltage corresponding to the phase difference signal. A second oscillator generates a second oscillation frequency signal having an oscillation frequency according to a second control signal originated from the first control signal, having one of a current and a voltage. A detection circuit generates a detection signal by detecting one of the current and the voltage of the first control signal. A signal generation circuit is connected to the detection circuit to generate a signal for changing the oscillation frequency of the first oscillator such that one of the current and the voltage of the second control signal is within a predetermined range in accordance with the detection signal.
Other aspects and advantages of the invention will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.